1. Field of the Invention
The present invention relates to a semiconductor integrated circuit operated by an instruction program stored to a built-in memory, and particularly relates to a semiconductor integrated circuit with an error detecting circuit capable of accurately detecting an operating error of an instruction memory.
2. Description of the Prior Art
FIG. 1 is a block diagram showing the construction of a conventional semiconductor integrated circuit. As shown in FIG. 1, the conventional integrated circuit has a program counter 1, an instruction ROM 2, an instruction register 5 and a decoder 8. A clock signal 101 and an instruction address signal 103 are inputted to the program counter 1. The program counter (first memory) 1 sets an address by an input of the instruction address signal 103. The program counter 1 is a circuit for sequentially outputting an address signal 104 to the instruction ROM 2 in synchronization with the clock signal 101 and storing the address signal 104. The program counter 1 is constructed by a register. An instruction code of a program is stored to the instruction ROM 2 in advance. The instruction ROM 2 is an instruction memory for outputting an instruction code signal 105 to the instruction register 5 in accordance with the address signal 104 and is constructed by a ROM (read only memory).
The clock signal 101 and the instruction code signal 105 are inputted to the instruction register 5. The instruction register (second memory) 5 is a circuit for temporarily storing the instruction code signal 105 in synchronization with the clock signal 101 and outputting an instruction data signal 113 to the decoder 8. The instruction register 5 is constructed by a register. The decoder 8 decodes the inputted instruction data signal 113 and outputs a unit control signal 117 for controlling the operation of an instruction executing unit of the semiconductor integrated circuit. For example, such a semiconductor integrated circuit is widely used in a microcomputer, etc.
An operation of the conventional semiconductor integrated circuit constructed above will next be explained. First, an instruction address signal 103 is inputted to the program counter 1. Thus, the program counter 1 sets an address and sequentially outputs an address signal 104 in synchronization with a clock signal 101. Next, when the address signal 104 is inputted to the instruction ROM 2, an instruction code stored to the instruction ROM 2 is read by designating an address signal. The instruction ROM 2 then outputs the instruction code to the instruction register 5 as an instruction code signal 105.
The instruction register 5 temporarily stores the instruction code signal 105 in synchronization with the clock signal 101. An instruction stored to the instruction register 5 is outputted from the instruction register 5 as an instruction data signal 113 and is then inputted to the decoder 8. The decoder 8 decodes the inputted instruction data signal 113 and generates a unit control signal 117 and outputs the unit control signal 117. The operation of the instruction executing unit of the semiconductor integrated circuit is controlled by the outputted unit control signal 117.
In the conventional semiconductor integrated circuit constructed in this way, when an instruction stored to the instruction ROM 2 has an error, the instruction register 5 stores the instruction having the error and the decoder 8 generates the unit control signal 117 on the basis of this instruction. Then, the operation of the instruction executing unit of the semiconductor integrated circuit is controlled by the unit control signal 117.
However, since the instruction based on the unit control signal 117 has the error, the operation of the instruction executing unit of the semiconductor integrated circuit is different from an expected operation so that an error in operation is caused. When the semiconductor integrated circuit is incorrectly operated by the error in instruction stored to the instruction ROM 2, it is difficult to analyze a cause of this incorrect operation. In particular, an extremely long time is required to analyze this cause since the error in the instruction memory shows various kinds of failure modes.
Therefore, for example, a memory tester having a built-in integrated circuit is disclosed in Japanese Unexamined Publication (KOKAI) No. Sho 63-18597 as a semiconductor integrated circuit capable of detecting an error in memory data. FIG. 2 is a block diagram showing the structure of the memory tester having the built-in integrated circuit. An integrated circuit 21 has a scan path control circuit 31, a memory address register 34, a memory 36 with parity, a parity check circuit 37 and a memory data register 39.
The scan path control circuit 31 is a circuit for outputting a scan path control signal 32 in accordance with a signal inputted from a scan path signal input pin group 30 and controlling the operations of registers (a memory address register 34 and a memory data register 39) constituting a scan path. A scan path input data pin 33 inputs data to the scan path. The memory address register 34 has a reset function for clearing data by a signal inputted from a reset signal input pin 35 and is constructed by a counter and a shift register. A signal on an address data parallel input line 22 is inputted to the memory address register 34 and a signal on an address data parallel output line 24 is outputted from the memory address register 34 and is inputted to the memory 36 with parity.
Data adding a parity bit thereto are stored to the memory 36 with parity. Data outputted from the memory 36 with parity are inputted to the parity check circuit 37 and the memory data register 39. The parity check circuit 37 performs a parity check for detecting an error and makes a correct or incorrect judgment and outputs a count enable signal 38 to the memory address register 34. Then, count-up of the memory address register 34 is inhibited by the count enable signal 38.
Further, a memory data parallel input line 26 and a memory data parallel output line 28 are connected to the memory data register 39. Data outputted from the memory 36 with parity are inputted to the memory data register 39 through the memory data parallel input line 26. The memory data register 39 is a circuit for latching output data from the memory 36 with parity and has a shift register function. A scan data line 40 connects an output of the memory address register 34 at a final stage thereof to an initial stage of the memory data register. Data of the memory data register 39 at a final stage thereof are outputted from a scan path output pin 41.
An operation of the integrated circuit 21 thus constructed will next be explained. First, the memory address register 34 is set to an all "zero" initial state by the reset signal input pin 35. Next, when a predetermined input signal is inputted from the scan path control signal input pin group 30 to the scan path control circuit 31, the scan path control circuit 31 counts up the memory address register 34 by a scan path control signal 32. Output data from the memory 36 with parity are inputted to the parity check circuit 37 every this count-up. Thus, it is judged whether the memory data are correct or incorrect. At this time, the output data from the memory 36 with parity are stored to the memory data register 39. The count-up of the memory address register 34 is continued if the output data are normal as a result of the correct or incorrect judgment in the parity check circuit 37. Thereafter, all address data of the memory 36 with parity are similarly judged.
In contrast to this, when the output data are incorrect as the result of the correct or incorrect judgment in the parity check circuit 37, the parity check circuit 37 inhibits the count-up of the memory address register 34. At this time, an address of data of the memory 36 with parity causing the error is latched to the memory address register 34, and the data of the memory 36 with parity causing the error are latched to the memory data register 39. Accordingly, the memory address register 34 and the memory data register 39 constitutes a scan path construction by inputting a predetermined signal from the scan path control signal input pin group 30 to the scan path control circuit 31. Thereafter, the address and the data stored to the memory address register 34 and the memory data register 39 are outputted from the scan path output pin 41 so that error information can be observed.
In the integrated circuit 21, arbitrary data of the memory 36 with parity can be observed by using the scan path constructed by the memory address register 34 and the memory data register 39. Namely, an arbitrary address is set to the memory address register 34 by inputting data from the scan path input data pin 33 to the memory address register 34. Thereafter, arbitrary data in the memory 36 with parity are outputted from the scan path output pin 41. By this, the arbitrary data of the memory 36 with parity can be observed.
However, in the above conventional integrated circuit 21, memory data are sequentially read by an address regularly changed so that error depending on an irregular change in address at an application operating time of a user can not be detected.
The error depending on the change in address will be described. Namely, when a memory area is divided into three banks or more and data of another bank are read by jumping one bank or more, the delay of an address decode caused by a change in address from one address to another address is increased when data are read from one bank and data are then read from another bank. Thus, data can not be read within a predetermined operating frequency so that an error is caused.
In the conventional integrated circuit, no address information is checked when an error in memory output data is detected. Accordingly, when contents at an address except for a designated address are read and incorrect data are read by a failure on a word line within a memory and so forth, an error check circuit judges the read data as normal data. As a result, error can not be accurately detected.
Since an error in data themselves read from the memory is detected in the conventional integrated circuit, a delay time from the memory to a register for storing these data is longer than a delay time from the memory to the error check circuit. Accordingly, when a register can not store data within a predetermined operating frequency, data read from the memory can not be stored and an error in operation is caused even if these data are judged as normal data. Accordingly, error can not be accurately detected.
As a result, address causing the error in operation can not be specified at an error generating time. Also, when one word of the memory is constructed by plural bits, bit position of the read data causing the error can not be specified. Accordingly, it is impossible to judge whether the error is caused since each circuit does not normally function, or the error is caused by a defect in manufacture. Thus, an extremely long time is required to analyze the error.
Further, since no application program is operated at an error detecting time, it is impossible to confirm whether an application program subsequent to a cycle having the detected error is normally operated. As a result, no countermeasures of the error can be taken and no normal operation can be confirmed so that reliability of a user is lost.